Flip-flops soft error rate evaluation approach considering internal single-event transient

High-speed Energy-efficient Soft Error Tolerant Flip-flops

Analysis of Soft Error Rate in Flip - Flops and Scannable Latches

the critical charge by increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating the various designs in 70 nm, 1V CMOS technology. Fir...

Study of Single Event Transient Error Mitigation

Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy groundlevel demands such as generic, flexible, efficient, and fast, are limited. The classic Triple Modular Redundancy (TMR) method is the most well-known and popular technique in space and nuclear environment...

Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design

1. Introduction As the clock frequency and circuit integrity have been increased exponentially, power consumption has also increased drastically and process variations have been becoming a big issue. One of the most effective methods for low power computation is dynamic voltage scaling (DVS) with in-situ timing-error detection. Furthermore, it is robust to parameter variations in the extremely ...

Single Edge Triggered Static D Flip-Flops: Performance Comparison

Due to fast growth of portable devices, power consumption and timing delays are the two important design parameters in high speed and low power VLSI design arena. In this paper we presents the comparison of single edge triggered static D flip-flop designs to show the benefit of power consumption ,delay and power delay product on the basis of area efficiency.